The present invention relates to a semiconductor memory and, more particularly, a high speed complementary MOS memory in which a signal level change is speeded up on data bus lines.
In a semiconductor memory device, improvement of access time may be attained by speeding up the change of a signal level on a data bus line. In fact, however, circuit elements such as FETs in a memory cell for effecting the signal level change have generally small current capacity and simultaneously the bus line has a parasitic capacitance. For this reason, the signal level appearing on the bus line changes slowly. This has been an obstacle to the improvement of access time in semiconductor memory devices.